temp_contoller_firmware/src_tests/tests/modbus_regs_file.cpp

#include "CppUTest/TestHarness.h"

extern "C"
{
    #include "modbus_regs_file.h"
}

#define U16_DATA_SIMPLE 0x3465
#define U16_DATA_MAX 0xFFFF
#define U16_DATA_ZERO 0x0000

#define ADDR_SIMPLE 0x0023
#define ADDR_MAX 0xFFFF
#define ADDR_ZERO 0x0000

TEST_GROUP(modbus_regs_file)
{
    uint16_t u16_data_simple;
    uint16_t u16_data_max;
    uint16_t u16_data_zero;

    void setup() {
        u16_data_simple = U16_DATA_SIMPLE;
        u16_data_max = U16_DATA_MAX;
        u16_data_zero = U16_DATA_ZERO;
    }

    void teardown() {
       MBRF_clear_file();
    }

};

// TEST(modbus_regs_file, read_wire_non_init_i_reg_zero_addr)
// {
//     MBRF_init_start();
//     CHECK_EQUAL(MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_input), MBR_OK);
//     CHECK_EQUAL(MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_input), MBR_OK);
//     MBRF_init_end();
// }

// TEST(modbus_regs_file, read_i_reg)
// {
//     MBRF_init_start();
//     MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_input);
//     MBRF_create_reg(ADDR_ZERO,&u16_data_zero,MBR_input);
//     MBRF_create_reg(ADDR_MAX,&u16_data_max,MBR_input);
//     MBRF_init_end();
//     uint16_t data;
//     CHECK_EQUAL(MBRF_read_reg(ADDR_SIMPLE,&data,MBR_input), MBR_OK);
//     CHECK_EQUAL(data,U16_DATA_SIMPLE);
//     CHECK_EQUAL(MBRF_read_reg(ADDR_ZERO,&data,MBR_input), MBR_OK);
//     CHECK_EQUAL(data,U16_DATA_ZERO);
//     CHECK_EQUAL(MBRF_read_reg(ADDR_MAX,&data,MBR_input), MBR_OK);
//     CHECK_EQUAL(data,U16_DATA_MAX);
// }

// TEST(modbus_regs_file, read_multiple_i_reg)
// {
//     #define START_ADDR 32u
//     #define PLUS 23u
//     uint16_t reg[6]={0,1,2,3,4,5};
//     MBRF_init_start();
//     //некрасиво но нормально 
//     MBRF_create_reg(START_ADDR,&reg[0],MBR_input);
//     MBRF_create_reg(START_ADDR+1,&reg[1],MBR_input);
//     MBRF_create_reg(START_ADDR+2,&reg[2],MBR_input);
//     MBRF_create_reg(START_ADDR+3,&reg[3],MBR_input);
//     MBRF_init_end();
//     uint8_t data[8]={0};
//     CHECK_EQUAL(MBRF_multiple_read_reg(START_ADDR, 4, data, MBR_input), MBR_OK);

//     CHECK_EQUAL(data[0],(uint8_t)((reg[0])>>8));
//     CHECK_EQUAL(data[1],(uint8_t)(reg[0]));
//     CHECK_EQUAL(data[2],(uint8_t)((reg[1])>>8));
//     CHECK_EQUAL(data[3],(uint8_t)(reg[1]));
//     CHECK_EQUAL(data[4],(uint8_t)((reg[2])>>8));
//     CHECK_EQUAL(data[5],(uint8_t)(reg[2]));
//     CHECK_EQUAL(data[6],(uint8_t)((reg[3])>>8));
//     CHECK_EQUAL(data[7],(uint8_t)(reg[3]));
// }


TEST(modbus_regs_file, read_wire_non_init_i_reg_zero_addr)
{
    MBRF_init_start();
    MBRF_init_end();
    uint16_t data=0;
    CHECK_EQUAL(MBRF_write_reg(ADDR_ZERO,data,MBR_input), MBR_ERROR);
    CHECK_EQUAL(MBRF_read_reg(ADDR_ZERO,&data,MBR_input), MBR_ERROR);
    CHECK_EQUAL(data,0);
}


///////////////////////////input////////////////////

TEST(modbus_regs_file, create_i_reg_before_init_file)
{
    CHECK_EQUAL(MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_input),MBR_CEATE_DISABLE);
}

TEST(modbus_regs_file, create_i_reg_defore_init_end)
{
    MBRF_init_start();
    CHECK_EQUAL(MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_input), MBR_OK);
    CHECK_EQUAL(MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_input), MBR_OK);
    MBRF_init_end();
    CHECK_EQUAL(MBRF_create_reg(ADDR_MAX,&u16_data_simple,MBR_input), MBR_CEATE_DISABLE);
}

TEST(modbus_regs_file, create_i_reg_simple)
{
    MBRF_init_start();
    CHECK_EQUAL(MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_input), MBR_OK);
    CHECK_EQUAL(MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_input), MBR_OK);
    CHECK_EQUAL(MBRF_create_reg(ADDR_MAX,&u16_data_simple,MBR_input), MBR_OK);
    CHECK_EQUAL(MBRF_init_end(), MBR_OK);
}

TEST(modbus_regs_file, create_i_reg_len_max)
{
    MBRF_init_start();
    for(uint32_t i=0; i<MBRF_MAX_QUANTITY(MBR_input);i++)
    {
       CHECK_EQUAL(MBRF_create_reg(i,&u16_data_simple,MBR_input), MBR_OK);
    }
    CHECK_EQUAL(MBRF_create_reg(ADDR_MAX,&u16_data_simple,MBR_input), MBR_LEN_ERROR);
    MBRF_init_end();
}

TEST(modbus_regs_file, create_2_i_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_input);
    MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_input);
    MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_input);
    CHECK_EQUAL(MBRF_init_end(),MBR_ADDR_ERROR);
}

TEST(modbus_regs_file, read_i_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_input);
    MBRF_create_reg(ADDR_ZERO,&u16_data_zero,MBR_input);
    MBRF_create_reg(ADDR_MAX,&u16_data_max,MBR_input);
    MBRF_init_end();
    uint16_t data;
    CHECK_EQUAL(MBRF_read_reg(ADDR_SIMPLE,&data,MBR_input), MBR_OK);
    CHECK_EQUAL(data,U16_DATA_SIMPLE);
    CHECK_EQUAL(MBRF_read_reg(ADDR_ZERO,&data,MBR_input), MBR_OK);
    CHECK_EQUAL(data,U16_DATA_ZERO);
    CHECK_EQUAL(MBRF_read_reg(ADDR_MAX,&data,MBR_input), MBR_OK);
    CHECK_EQUAL(data,U16_DATA_MAX);
}

TEST(modbus_regs_file, read_wire_non_init_i_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_input);
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_zero,MBR_input);
    MBRF_init_end();
    uint16_t data=0;
    CHECK_EQUAL(MBRF_write_reg(ADDR_MAX,data,MBR_input), MBR_ERROR);
    CHECK_EQUAL(MBRF_read_reg(ADDR_MAX,&data,MBR_input), MBR_ERROR);
    CHECK_EQUAL(data,0);
}

TEST(modbus_regs_file, write_i_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_input);
    MBRF_create_reg(ADDR_ZERO,&u16_data_zero,MBR_input);
    MBRF_create_reg(ADDR_MAX,&u16_data_max,MBR_input);
    MBRF_init_end();
    uint16_t data_w=(U16_DATA_ZERO+0x675);//random num
    uint16_t data_r;
    CHECK_EQUAL(MBRF_write_reg(ADDR_ZERO,data_w,MBR_input), MBR_OK);
    MBRF_read_reg(ADDR_ZERO,&data_r,MBR_input);
    CHECK_EQUAL(data_r,data_w);
}

TEST(modbus_regs_file, read_multiple_i_reg)
{
    #define START_ADDR 32u
    #define PLUS 23u
    uint16_t reg[6]={0,1,2,3,4,5};
    MBRF_init_start();
    //некрасиво но нормально 
    MBRF_create_reg(START_ADDR,&reg[0],MBR_input);
    MBRF_create_reg(START_ADDR+1,&reg[1],MBR_input);
    MBRF_create_reg(START_ADDR+2,&reg[2],MBR_input);
    MBRF_create_reg(START_ADDR+3,&reg[3],MBR_input);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(START_ADDR, 4, data, MBR_input), MBR_OK);

    CHECK_EQUAL(data[0],(uint8_t)((reg[0])>>8));
    CHECK_EQUAL(data[1],(uint8_t)(reg[0]));
    CHECK_EQUAL(data[2],(uint8_t)((reg[1])>>8));
    CHECK_EQUAL(data[3],(uint8_t)(reg[1]));
    CHECK_EQUAL(data[4],(uint8_t)((reg[2])>>8));
    CHECK_EQUAL(data[5],(uint8_t)(reg[2]));
    CHECK_EQUAL(data[6],(uint8_t)((reg[3])>>8));
    CHECK_EQUAL(data[7],(uint8_t)(reg[3]));
}

TEST(modbus_regs_file, read_multiple_i_reg_zero_len)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_ZERO,&u16_data_zero,MBR_input);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(ADDR_ZERO, 0, data, MBR_input), MBR_LEN_ERROR);
}

TEST(modbus_regs_file, read_multiple_i_reg_one_len)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_input);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(ADDR_SIMPLE, 1, data, MBR_input), MBR_OK);
    CHECK_EQUAL(data[0],(uint8_t)(U16_DATA_SIMPLE>>8));
    CHECK_EQUAL(data[1],(uint8_t)(U16_DATA_SIMPLE));
    CHECK_EQUAL(data[2],0);
    CHECK_EQUAL(data[3],0);
    CHECK_EQUAL(data[4],0);
    CHECK_EQUAL(data[5],0);
    CHECK_EQUAL(data[6],0);
    CHECK_EQUAL(data[7],0);
}

TEST(modbus_regs_file, read_multiple_window_i_reg)
{
    #define START_ADDR 32u
    #define PLUS 23u

    uint16_t buf=1;
    MBRF_init_start();
    //некрасиво но нормально 
    MBRF_create_reg(START_ADDR,&buf,MBR_input);
    MBRF_create_reg(START_ADDR+1,&buf,MBR_input);
    MBRF_create_reg(START_ADDR+3,&buf,MBR_input);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(START_ADDR, 3, data, MBR_input), MBR_ERROR);
    CHECK_EQUAL(data[0],0);
    CHECK_EQUAL(data[1],0);
    CHECK_EQUAL(data[2],0);
    CHECK_EQUAL(data[3],0);
    CHECK_EQUAL(data[4],0);
    CHECK_EQUAL(data[5],0);
    CHECK_EQUAL(data[6],0);
    CHECK_EQUAL(data[7],0);
}

TEST(modbus_regs_file, read_multiple_non_create_i_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_input);
    MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_input);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(ADDR_MAX, 1, data, MBR_input), MBR_ERROR);
    CHECK_EQUAL(data[0],0);
    CHECK_EQUAL(data[1],0);
    CHECK_EQUAL(data[2],0);
    CHECK_EQUAL(data[3],0);
    CHECK_EQUAL(data[4],0);
    CHECK_EQUAL(data[5],0);
    CHECK_EQUAL(data[6],0);
    CHECK_EQUAL(data[7],0);
}

///////////////////////////holding////////////////////

TEST(modbus_regs_file, create_h_reg_before_init_file)
{
    CHECK_EQUAL(MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_holding),MBR_CEATE_DISABLE);
}

TEST(modbus_regs_file, create_h_reg_defore_init_end)
{
    MBRF_init_start();
    CHECK_EQUAL(MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_holding), MBR_OK);
    CHECK_EQUAL(MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_holding), MBR_OK);
    MBRF_init_end();
    CHECK_EQUAL(MBRF_create_reg(ADDR_MAX,&u16_data_simple,MBR_holding), MBR_CEATE_DISABLE);
}

TEST(modbus_regs_file, create_h_reg_simple)
{
    MBRF_init_start();
    CHECK_EQUAL(MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_holding), MBR_OK);
    CHECK_EQUAL(MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_holding), MBR_OK);
    CHECK_EQUAL(MBRF_create_reg(ADDR_MAX,&u16_data_simple,MBR_holding), MBR_OK);
    CHECK_EQUAL(MBRF_init_end(), MBR_OK);
}

TEST(modbus_regs_file, create_h_reg_len_max)
{
    MBRF_init_start();
    for(uint32_t i=0; i<MBRF_MAX_QUANTITY(MBR_holding);i++)
    {
       CHECK_EQUAL(MBRF_create_reg(i,&u16_data_simple,MBR_holding), MBR_OK);
    }
    CHECK_EQUAL(MBRF_create_reg(ADDR_MAX,&u16_data_simple,MBR_holding), MBR_LEN_ERROR);
    MBRF_init_end();
}

TEST(modbus_regs_file, create_2_h_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_holding);
    MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_holding);
    MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_holding);
    CHECK_EQUAL(MBRF_init_end(),MBR_ADDR_ERROR);
}

TEST(modbus_regs_file, read_h_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_holding);
    MBRF_create_reg(ADDR_ZERO,&u16_data_zero,MBR_holding);
    MBRF_create_reg(ADDR_MAX,&u16_data_max,MBR_holding);
    MBRF_init_end();
    uint16_t data;
    CHECK_EQUAL(MBRF_read_reg(ADDR_SIMPLE,&data,MBR_holding), MBR_OK);
    CHECK_EQUAL(data,U16_DATA_SIMPLE);
    CHECK_EQUAL(MBRF_read_reg(ADDR_ZERO,&data,MBR_holding), MBR_OK);
    CHECK_EQUAL(data,U16_DATA_ZERO);
    CHECK_EQUAL(MBRF_read_reg(ADDR_MAX,&data,MBR_holding), MBR_OK);
    CHECK_EQUAL(data,U16_DATA_MAX);
}

TEST(modbus_regs_file, read_wire_non_init_h_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_holding);
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_zero,MBR_holding);
    MBRF_init_end();
    uint16_t data=0;
    CHECK_EQUAL(MBRF_write_reg(ADDR_MAX,data,MBR_holding), MBR_ERROR);
    CHECK_EQUAL(MBRF_read_reg(ADDR_MAX,&data,MBR_holding), MBR_ERROR);
    CHECK_EQUAL(data,0);
}

TEST(modbus_regs_file, write_h_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_holding);
    MBRF_create_reg(ADDR_ZERO,&u16_data_zero,MBR_holding);
    MBRF_create_reg(ADDR_MAX,&u16_data_max,MBR_holding);
    MBRF_init_end();
    uint16_t data_w=(U16_DATA_ZERO+0x675);//random num
    uint16_t data_r;
    CHECK_EQUAL(MBRF_write_reg(ADDR_ZERO,data_w,MBR_holding), MBR_OK);
    MBRF_read_reg(ADDR_ZERO,&data_r,MBR_holding);
    CHECK_EQUAL(data_r,data_w);
}

TEST(modbus_regs_file, read_multiple_h_reg)
{
    #define START_ADDR 32u
    #define PLUS 23u
    uint16_t reg[6]={0,1,2,3,4,5};
    MBRF_init_start();
    //некрасиво но нормально 
    MBRF_create_reg(START_ADDR,&reg[0],MBR_holding);
    MBRF_create_reg(START_ADDR+1,&reg[1],MBR_holding);
    MBRF_create_reg(START_ADDR+2,&reg[2],MBR_holding);
    MBRF_create_reg(START_ADDR+3,&reg[3],MBR_holding);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(START_ADDR, 4, data, MBR_holding), MBR_OK);

    CHECK_EQUAL(data[0],(uint8_t)((reg[0])>>8));
    CHECK_EQUAL(data[1],(uint8_t)(reg[0]));
    CHECK_EQUAL(data[2],(uint8_t)((reg[1])>>8));
    CHECK_EQUAL(data[3],(uint8_t)(reg[1]));
    CHECK_EQUAL(data[4],(uint8_t)((reg[2])>>8));
    CHECK_EQUAL(data[5],(uint8_t)(reg[2]));
    CHECK_EQUAL(data[6],(uint8_t)((reg[3])>>8));
    CHECK_EQUAL(data[7],(uint8_t)(reg[3]));
}

TEST(modbus_regs_file, read_multiple_h_reg_zero_len)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_ZERO,&u16_data_zero,MBR_holding);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(ADDR_ZERO, 0, data, MBR_holding), MBR_LEN_ERROR);
}

TEST(modbus_regs_file, read_multiple_h_reg_one_len)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_holding);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(ADDR_SIMPLE, 1, data, MBR_holding), MBR_OK);
    CHECK_EQUAL(data[0],(uint8_t)(U16_DATA_SIMPLE>>8));
    CHECK_EQUAL(data[1],(uint8_t)(U16_DATA_SIMPLE));
    CHECK_EQUAL(data[2],0);
    CHECK_EQUAL(data[3],0);
    CHECK_EQUAL(data[4],0);
    CHECK_EQUAL(data[5],0);
    CHECK_EQUAL(data[6],0);
    CHECK_EQUAL(data[7],0);
}

TEST(modbus_regs_file, read_multiple_window_h_reg)
{
    #define START_ADDR 32u
    #define PLUS 23u

    uint16_t buf=1;
    MBRF_init_start();
    //некрасиво но нормально 
    MBRF_create_reg(START_ADDR,&buf,MBR_holding);
    MBRF_create_reg(START_ADDR+1,&buf,MBR_holding);
    MBRF_create_reg(START_ADDR+3,&buf,MBR_holding);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(START_ADDR, 3, data, MBR_holding), MBR_ERROR);
    CHECK_EQUAL(data[0],0);
    CHECK_EQUAL(data[1],0);
    CHECK_EQUAL(data[2],0);
    CHECK_EQUAL(data[3],0);
    CHECK_EQUAL(data[4],0);
    CHECK_EQUAL(data[5],0);
    CHECK_EQUAL(data[6],0);
    CHECK_EQUAL(data[7],0);
}

TEST(modbus_regs_file, read_multiple_non_create_h_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_holding);
    MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_holding);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(ADDR_MAX, 1, data, MBR_holding), MBR_ERROR);
    CHECK_EQUAL(data[0],0);
    CHECK_EQUAL(data[1],0);
    CHECK_EQUAL(data[2],0);
    CHECK_EQUAL(data[3],0);
    CHECK_EQUAL(data[4],0);
    CHECK_EQUAL(data[5],0);
    CHECK_EQUAL(data[6],0);
    CHECK_EQUAL(data[7],0);
}

///////////////////////////input_discrete////////////////////

TEST(modbus_regs_file, create_id_reg_before_init_file)
{
    CHECK_EQUAL(MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_input_discrete),MBR_CEATE_DISABLE);
}

TEST(modbus_regs_file, create_id_reg_defore_init_end)
{
    MBRF_init_start();
    CHECK_EQUAL(MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_input_discrete), MBR_OK);
    CHECK_EQUAL(MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_input_discrete), MBR_OK);
    MBRF_init_end();
    CHECK_EQUAL(MBRF_create_reg(ADDR_MAX,&u16_data_simple,MBR_input_discrete), MBR_CEATE_DISABLE);
}

TEST(modbus_regs_file, create_id_reg_simple)
{
    MBRF_init_start();
    CHECK_EQUAL(MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_input_discrete), MBR_OK);
    CHECK_EQUAL(MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_input_discrete), MBR_OK);
    CHECK_EQUAL(MBRF_create_reg(ADDR_MAX,&u16_data_simple,MBR_input_discrete), MBR_OK);
    CHECK_EQUAL(MBRF_init_end(), MBR_OK);
}

TEST(modbus_regs_file, create_id_reg_len_max)
{
    MBRF_init_start();
    for(uint32_t i=0; i<MBRF_MAX_QUANTITY(MBR_input_discrete);i++)
    {
       CHECK_EQUAL(MBRF_create_reg(i,&u16_data_simple,MBR_input_discrete), MBR_OK);
    }
    CHECK_EQUAL(MBRF_create_reg(ADDR_MAX,&u16_data_simple,MBR_input_discrete), MBR_LEN_ERROR);
    MBRF_init_end();
}

TEST(modbus_regs_file, create_2_id_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_input_discrete);
    MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_input_discrete);
    MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_input_discrete);
    CHECK_EQUAL(MBRF_init_end(),MBR_ADDR_ERROR);
}

TEST(modbus_regs_file, read_id_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_input_discrete);
    MBRF_create_reg(ADDR_ZERO,&u16_data_zero,MBR_input_discrete);
    MBRF_create_reg(ADDR_MAX,&u16_data_max,MBR_input_discrete);
    MBRF_init_end();
    uint16_t data;
    CHECK_EQUAL(MBRF_read_reg(ADDR_SIMPLE,&data,MBR_input_discrete), MBR_OK);
    CHECK_EQUAL(data,U16_DATA_SIMPLE);
    CHECK_EQUAL(MBRF_read_reg(ADDR_ZERO,&data,MBR_input_discrete), MBR_OK);
    CHECK_EQUAL(data,U16_DATA_ZERO);
    CHECK_EQUAL(MBRF_read_reg(ADDR_MAX,&data,MBR_input_discrete), MBR_OK);
    CHECK_EQUAL(data,U16_DATA_MAX);
}

TEST(modbus_regs_file, read_wire_non_init_id_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_input_discrete);
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_zero,MBR_input_discrete);
    MBRF_init_end();
    uint16_t data=0;
    CHECK_EQUAL(MBRF_write_reg(ADDR_MAX,data,MBR_input_discrete), MBR_ERROR);
    CHECK_EQUAL(MBRF_read_reg(ADDR_MAX,&data,MBR_input_discrete), MBR_ERROR);
    CHECK_EQUAL(data,0);
}

TEST(modbus_regs_file, write_id_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_input_discrete);
    MBRF_create_reg(ADDR_ZERO,&u16_data_zero,MBR_input_discrete);
    MBRF_create_reg(ADDR_MAX,&u16_data_max,MBR_input_discrete);
    MBRF_init_end();
    uint16_t data_w=(U16_DATA_ZERO+0x675);//random num
    uint16_t data_r;
    CHECK_EQUAL(MBRF_write_reg(ADDR_ZERO,data_w,MBR_input_discrete), MBR_OK);
    MBRF_read_reg(ADDR_ZERO,&data_r,MBR_input_discrete);
    CHECK_EQUAL(data_r,data_w);
}

TEST(modbus_regs_file, read_multiple_id_reg)
{
    #define START_ADDR 32u
    #define PLUS 23u
    uint16_t reg[6]={0,1,2,3,4,5};
    MBRF_init_start();
    //некрасиво но нормально 
    MBRF_create_reg(START_ADDR,&reg[0],MBR_input_discrete);
    MBRF_create_reg(START_ADDR+1,&reg[1],MBR_input_discrete);
    MBRF_create_reg(START_ADDR+2,&reg[2],MBR_input_discrete);
    MBRF_create_reg(START_ADDR+3,&reg[3],MBR_input_discrete);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(START_ADDR, 4, data, MBR_input_discrete), MBR_OK);

    CHECK_EQUAL(data[0],(uint8_t)((reg[0])>>8));
    CHECK_EQUAL(data[1],(uint8_t)(reg[0]));
    CHECK_EQUAL(data[2],(uint8_t)((reg[1])>>8));
    CHECK_EQUAL(data[3],(uint8_t)(reg[1]));
    CHECK_EQUAL(data[4],(uint8_t)((reg[2])>>8));
    CHECK_EQUAL(data[5],(uint8_t)(reg[2]));
    CHECK_EQUAL(data[6],(uint8_t)((reg[3])>>8));
    CHECK_EQUAL(data[7],(uint8_t)(reg[3]));
}

TEST(modbus_regs_file, read_multiple_id_reg_zero_len)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_ZERO,&u16_data_zero,MBR_input_discrete);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(ADDR_ZERO, 0, data, MBR_input_discrete), MBR_LEN_ERROR);
}

TEST(modbus_regs_file, read_multiple_id_reg_one_len)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_input_discrete);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(ADDR_SIMPLE, 1, data, MBR_input_discrete), MBR_OK);
    CHECK_EQUAL(data[0],(uint8_t)(U16_DATA_SIMPLE>>8));
    CHECK_EQUAL(data[1],(uint8_t)(U16_DATA_SIMPLE));
    CHECK_EQUAL(data[2],0);
    CHECK_EQUAL(data[3],0);
    CHECK_EQUAL(data[4],0);
    CHECK_EQUAL(data[5],0);
    CHECK_EQUAL(data[6],0);
    CHECK_EQUAL(data[7],0);
}

TEST(modbus_regs_file, read_multiple_window_id_reg)
{
    #define START_ADDR 32u
    #define PLUS 23u

    uint16_t buf=1;
    MBRF_init_start();
    //некрасиво но нормально 
    MBRF_create_reg(START_ADDR,&buf,MBR_input_discrete);
    MBRF_create_reg(START_ADDR+1,&buf,MBR_input_discrete);
    MBRF_create_reg(START_ADDR+3,&buf,MBR_input_discrete);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(START_ADDR, 3, data, MBR_input_discrete), MBR_ERROR);
    CHECK_EQUAL(data[0],0);
    CHECK_EQUAL(data[1],0);
    CHECK_EQUAL(data[2],0);
    CHECK_EQUAL(data[3],0);
    CHECK_EQUAL(data[4],0);
    CHECK_EQUAL(data[5],0);
    CHECK_EQUAL(data[6],0);
    CHECK_EQUAL(data[7],0);
}

TEST(modbus_regs_file, read_multiple_non_create_id_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_input_discrete);
    MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_input_discrete);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(ADDR_MAX, 1, data, MBR_input_discrete), MBR_ERROR);
    CHECK_EQUAL(data[0],0);
    CHECK_EQUAL(data[1],0);
    CHECK_EQUAL(data[2],0);
    CHECK_EQUAL(data[3],0);
    CHECK_EQUAL(data[4],0);
    CHECK_EQUAL(data[5],0);
    CHECK_EQUAL(data[6],0);
    CHECK_EQUAL(data[7],0);
}

///////////////////////////coils////////////////////

TEST(modbus_regs_file, create_c_reg_before_init_file)
{
    CHECK_EQUAL(MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_coils),MBR_CEATE_DISABLE);
}

TEST(modbus_regs_file, create_c_reg_defore_init_end)
{
    MBRF_init_start();
    CHECK_EQUAL(MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_coils), MBR_OK);
    CHECK_EQUAL(MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_coils), MBR_OK);
    MBRF_init_end();
    CHECK_EQUAL(MBRF_create_reg(ADDR_MAX,&u16_data_simple,MBR_coils), MBR_CEATE_DISABLE);
}

TEST(modbus_regs_file, create_c_reg_simple)
{
    MBRF_init_start();
    CHECK_EQUAL(MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_coils), MBR_OK);
    CHECK_EQUAL(MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_coils), MBR_OK);
    CHECK_EQUAL(MBRF_create_reg(ADDR_MAX,&u16_data_simple,MBR_coils), MBR_OK);
    CHECK_EQUAL(MBRF_init_end(), MBR_OK);
}

TEST(modbus_regs_file, create_c_reg_len_max)
{
    MBRF_init_start();
    for(uint32_t i=0; i<MBRF_MAX_QUANTITY(MBR_coils);i++)
    {
       CHECK_EQUAL(MBRF_create_reg(i,&u16_data_simple,MBR_coils), MBR_OK);
    }
    CHECK_EQUAL(MBRF_create_reg(ADDR_MAX,&u16_data_simple,MBR_coils), MBR_LEN_ERROR);
    MBRF_init_end();
}

TEST(modbus_regs_file, create_2_c_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_coils);
    MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_coils);
    MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_coils);
    CHECK_EQUAL(MBRF_init_end(),MBR_ADDR_ERROR);
}

TEST(modbus_regs_file, read_c_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_coils);
    MBRF_create_reg(ADDR_ZERO,&u16_data_zero,MBR_coils);
    MBRF_create_reg(ADDR_MAX,&u16_data_max,MBR_coils);
    MBRF_init_end();
    uint16_t data;
    CHECK_EQUAL(MBRF_read_reg(ADDR_SIMPLE,&data,MBR_coils), MBR_OK);
    CHECK_EQUAL(data,U16_DATA_SIMPLE);
    CHECK_EQUAL(MBRF_read_reg(ADDR_ZERO,&data,MBR_coils), MBR_OK);
    CHECK_EQUAL(data,U16_DATA_ZERO);
    CHECK_EQUAL(MBRF_read_reg(ADDR_MAX,&data,MBR_coils), MBR_OK);
    CHECK_EQUAL(data,U16_DATA_MAX);
}

TEST(modbus_regs_file, read_wire_non_init_c_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_coils);
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_zero,MBR_coils);
    MBRF_init_end();
    uint16_t data=0;
    CHECK_EQUAL(MBRF_write_reg(ADDR_MAX,data,MBR_coils), MBR_ERROR);
    CHECK_EQUAL(MBRF_read_reg(ADDR_MAX,&data,MBR_coils), MBR_ERROR);
    CHECK_EQUAL(data,0);
}

TEST(modbus_regs_file, write_c_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_coils);
    MBRF_create_reg(ADDR_ZERO,&u16_data_zero,MBR_coils);
    MBRF_create_reg(ADDR_MAX,&u16_data_max,MBR_coils);
    MBRF_init_end();
    uint16_t data_w=(U16_DATA_ZERO+0x675);//random num
    uint16_t data_r;
    CHECK_EQUAL(MBRF_write_reg(ADDR_ZERO,data_w,MBR_coils), MBR_OK);
    MBRF_read_reg(ADDR_ZERO,&data_r,MBR_coils);
    CHECK_EQUAL(data_r,data_w);
}

TEST(modbus_regs_file, read_multiple_c_reg)
{
    #define START_ADDR 32u
    #define PLUS 23u
    uint16_t reg[6]={0,1,2,3,4,5};
    MBRF_init_start();
    //некрасиво но нормально 
    MBRF_create_reg(START_ADDR,&reg[0],MBR_coils);
    MBRF_create_reg(START_ADDR+1,&reg[1],MBR_coils);
    MBRF_create_reg(START_ADDR+2,&reg[2],MBR_coils);
    MBRF_create_reg(START_ADDR+3,&reg[3],MBR_coils);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(START_ADDR, 4, data, MBR_coils), MBR_OK);

    CHECK_EQUAL(data[0],(uint8_t)((reg[0])>>8));
    CHECK_EQUAL(data[1],(uint8_t)(reg[0]));
    CHECK_EQUAL(data[2],(uint8_t)((reg[1])>>8));
    CHECK_EQUAL(data[3],(uint8_t)(reg[1]));
    CHECK_EQUAL(data[4],(uint8_t)((reg[2])>>8));
    CHECK_EQUAL(data[5],(uint8_t)(reg[2]));
    CHECK_EQUAL(data[6],(uint8_t)((reg[3])>>8));
    CHECK_EQUAL(data[7],(uint8_t)(reg[3]));
}

TEST(modbus_regs_file, read_multiple_c_reg_zero_len)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_ZERO,&u16_data_zero,MBR_coils);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(ADDR_ZERO, 0, data, MBR_coils), MBR_LEN_ERROR);
}

TEST(modbus_regs_file, read_multiple_c_reg_one_len)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_coils);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(ADDR_SIMPLE, 1, data, MBR_coils), MBR_OK);
    CHECK_EQUAL(data[0],(uint8_t)(U16_DATA_SIMPLE>>8));
    CHECK_EQUAL(data[1],(uint8_t)(U16_DATA_SIMPLE));
    CHECK_EQUAL(data[2],0);
    CHECK_EQUAL(data[3],0);
    CHECK_EQUAL(data[4],0);
    CHECK_EQUAL(data[5],0);
    CHECK_EQUAL(data[6],0);
    CHECK_EQUAL(data[7],0);
}

TEST(modbus_regs_file, read_multiple_window_c_reg)
{
    #define START_ADDR 32u
    #define PLUS 23u

    uint16_t buf=1;
    MBRF_init_start();
    //некрасиво но нормально 
    MBRF_create_reg(START_ADDR,&buf,MBR_coils);
    MBRF_create_reg(START_ADDR+1,&buf,MBR_coils);
    MBRF_create_reg(START_ADDR+3,&buf,MBR_coils);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(START_ADDR, 3, data, MBR_coils), MBR_ERROR);
    CHECK_EQUAL(data[0],0);
    CHECK_EQUAL(data[1],0);
    CHECK_EQUAL(data[2],0);
    CHECK_EQUAL(data[3],0);
    CHECK_EQUAL(data[4],0);
    CHECK_EQUAL(data[5],0);
    CHECK_EQUAL(data[6],0);
    CHECK_EQUAL(data[7],0);
}

TEST(modbus_regs_file, read_multiple_non_create_c_reg)
{
    MBRF_init_start();
    MBRF_create_reg(ADDR_SIMPLE,&u16_data_simple,MBR_coils);
    MBRF_create_reg(ADDR_ZERO,&u16_data_simple,MBR_coils);
    MBRF_init_end();
    uint8_t data[8]={0};
    CHECK_EQUAL(MBRF_multiple_read_reg(ADDR_MAX, 1, data, MBR_coils), MBR_ERROR);
    CHECK_EQUAL(data[0],0);
    CHECK_EQUAL(data[1],0);
    CHECK_EQUAL(data[2],0);
    CHECK_EQUAL(data[3],0);
    CHECK_EQUAL(data[4],0);
    CHECK_EQUAL(data[5],0);
    CHECK_EQUAL(data[6],0);
    CHECK_EQUAL(data[7],0);
}